Pop package and method of fabricating the same

ABSTRACT

A method of fabricating a package-on-package (POP) package is disclosed. The method includes preparing a first semiconductor package including a first substrate having external contact electrodes and a first semiconductor chip mounted on the first substrate, and preparing a second semiconductor package including a second substrate having external contact electrodes and a second semiconductor chip mounted on the second substrate. The method further includes forming lead lines in the second semiconductor package, the lead lines being electrically connected to the external contact electrodes of the second substrate, and stacking the second semiconductor package on the first semiconductor package and electrically connecting the external contact electrodes of the first substrate to the external contact electrodes of the second substrate using the lead lines.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application is a divisional applicationof and claims priority to U.S. patent application Ser. No. 11/851,284filed Sep. 6, 2007, which claims priority under 35 U.S.C. §119 to KoreanPatent Application No. 10-2006-0085881, filed on Sep. 6, 2006, in theKorean Intellectual Property Office, the disclosure of each isincorporated herein in its entirety by reference.

BACKGROUND

1. Technical Field

The present invention relates to a package-on-package (POP) package anda fabricating method thereof, and more particularly, to a POP packagewhich is prevented from being short-circuited even when an underlyingsemiconductor package is thick and which can sufficiently withstanddeformation caused by post-fabrication warpage, and a fabricating methodthereof.

2. Description of the Related Art

In recent years, as electronic products have been incorporating greaterfunctionality, a number of devices need to be integrated in onesubstrate, which makes it difficult to achieve the desired compactnessof the products. Accordingly, researchers are currently seeking atechnique of integrating a number of devices in a limited space.

Mounting several chips in one semiconductor package is well known.Furthermore, a package-on-package (POP) package is well known in which apackage is formed on another package.

A conventional POP package will be described with reference to FIG. 15.A first semiconductor package 10 includes a first substrate 11 with asemiconductor chip (not shown) mounted thereon, a mold 14 for holdingthe semiconductor chip, and external contact electrodes 12 and solderballs 13 for connection to an external board.

A second semiconductor package 20 includes a second substrate 21 and asemiconductor chip (not shown) mounted thereon, a mold 24 for holdingthe semiconductor chip, and external contact electrodes 22 and solderballs 23 for connection to the underlying first semiconductor package10.

The second semiconductor package 20 is stacked on the firstsemiconductor package 10 and connected thereto through the solder balls23.

In the case where the first semiconductor package 10 is a multi-chippackage (MCP) in which several semiconductor chips are stacked, inaccordance with a recent trend, the mold 14 is thick and thus the solderballs connecting the first semiconductor package 10 to the secondsemiconductor package 20 should be large. Recently, as electronicproducts get more compact, packages get smaller, making it difficult tosecure a sufficient interval between the solder balls. In other words,as the solder balls become larger to accommodate the height of the moldin the lower package, it is difficult to achieve sufficient spacingbetween the solder balls to prevent shorts between them.

As a result, there is a problem in that the solder balls areshort-circuited, as shown in FIG. 16B. That is, the solder balls aredesired to be evenly arranged as shown in FIG. 16A, but instead, theyare lumped and short-circuited as shown in FIG. 16B.

In addition, a connection between stacked packages using solder ballscauses the following problems: A fabricated POP package may be bent dueto, for example, hardening or heating as time lapses and, in this case,a difference in warpage between the stacked semiconductor packages maycause disconnection between the packages, as shown in FIGS. 17A and 17B.

Accordingly, there is a need for a method for connection in a POPpackage which is capable of preventing short-circuits due to compactnessof products and allowing a semiconductor package to sufficientlywithstand deformation caused by post-fabrication warpage.

SUMMARY

The present invention provides a package-on-package (POP) package whichis prevented from being short-circuited between connection terminalseven when an underlying semiconductor package is thick and which cansufficiently withstand deformation caused by post-fabrication warpage.

The present invention also provides a method of fabricating a POPpackage which is prevented from being short-circuited between connectionterminals even when an underlying semiconductor package is thick andwhich can sufficiently withstand deformation caused by post-fabricationwarpage.

According to an aspect of the present invention, there is provided apackage-on-package (POP) package including a first semiconductor packageincluding a first substrate having external contact electrodes and afirst semiconductor chip mounted on the first substrate; a secondsemiconductor package including a second substrate having externalcontact electrodes and a second semiconductor chip mounted on the secondsubstrate, the second semiconductor package being located on the firstsemiconductor package; and lead lines for electrically connecting theexternal contact electrodes of the first substrate to the externalcontact electrodes of the second substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the accompanying drawings in which:

FIG. 1 illustrates a package-on-package (POP) package according to anembodiment of the present invention;

FIGS. 2A and 2B illustrate an end of a lead line of a POP packageaccording to an embodiment of the present invention;

FIG. 3A illustrates a POP package according to another embodiment of thepresent invention;

FIG. 3B illustrates a bent portion of the lead line of FIG. 3A;

FIGS. 4A and 4B illustrate a connection between an external contactelectrode of the first substrate and a lead line according to yetanother embodiment of the present invention;

FIG. 5 illustrates a POP package of the present invention mounted on anexternal board;

FIGS. 6A and 6B illustrate ends of lead lines when a POP package ismounted on an external board;

FIGS. 7A and 7B illustrate a lower surface of the second substrate andlead lines connected thereto according to some embodiments of thepresent invention, respectively;

FIG. 8 illustrates a POP package according to some embodiments of thepresent invention;

FIG. 9 is an exploded perspective view illustrating a process in which afirst semiconductor package and a second semiconductor package areconnected through lead lines according to an embodiment of the presentinvention;

FIGS. 10A through 10E sequentially illustrate a method for forming leadlines in a second semiconductor package according to an embodiment ofthe present invention;

FIG. 11 illustrates a lead frame for forming lead lines in a secondsemiconductor package according to an embodiment of the presentinvention;

FIGS. 12 and 13 illustrate a process of forming lead lines in externalcontact electrodes of the second semiconductor package using the leadframe of FIG. 11;

FIG. 14 illustrates a lead frame for forming lead lines in a secondsemiconductor package according to another embodiment of the presentinvention;

FIG. 15 illustrates a conventional POP package;

FIGS. 16A and 16B are enlarged photographs illustrating the layout ofnormal solder balls and the layout of short-circuited solder balls,respectively; and

FIGS. 17A and 17B illustrate a conventional POP package short-circuiteddue to warpage.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likenumbers refer to like elements throughout the specification.Furthermore, various elements and regions in the drawings are drawn in aschematic manner. Accordingly, the present invention is not limited byrelative sizes and intervals shown in the accompanying drawings.

FIG. 1 illustrates a package-on-package (POP) package according to anembodiment of the present invention.

A POP package according to an embodiment of the present inventionincludes a first semiconductor package 100 including a first substrate110 having external contact electrodes 120, and a first semiconductorchip 140 mounted on the first substrate 110. The first semiconductorchip 140 may be electrically connected with the first substrate 110 bywire bonding and held by a mold 130.

The POP package of the present invention further includes a secondsemiconductor package 200 including a second substrate 210 havingexternal contact electrodes 220 and a second semiconductor chip 240mounted on the second substrate 210. The second semiconductor chip 240may be electrically connected with the second substrate 210 by wirebonding and held by a mold 230. Further, the external contact electrodes220 may be slightly protruded from a lower surface 210 a of the secondsubstrate 210.

The first semiconductor package 100 and the second semiconductor package200 may be fabricated by a typical semiconductor-package fabricatingmethod. That is, the packages may be fabricated by bonding asemiconductor chip on a substrate, forming wire-bonding for thesemiconductor chip, and molding the semiconductor chip usingencapsulating resin. However, the present invention is not limitedthereto.

The second semiconductor package 200 is located on the firstsemiconductor package 100, and the external contact electrodes 120 ofthe first substrate 110 are connected with the external contactelectrodes 220 of the second substrate 210 through lead lines 300.

Referring to FIGS. 2A and 2B, the lead line 300 may be a bar having apolygonal cross-section such as a rectangular cross-section (asindicated by 300 a) or a pin having a circular cross-section (asindicated by 300 b). The lead line 300 has a length that may be properlyselected depending on the height of the first semiconductor package, butthe lead line 300 is not limited thereto.

The first semiconductor package 100 may be electrically connected withan underlying main board (not shown) via the external contact electrodes120 of the first substrate 110. The external contact electrodes 120 andthe main board may be connected to each other using, for example, solderballs but the present invention is not limited thereto.

The lead line 300 may have a form as shown in FIG. 3A. Referring to FIG.3A, the lead line 310 may be connected such that a portion of the leadline 310 is substantially parallel with the lower surface 210 a of thesecond substrate 210 in a position where the lead line 300 is connectedwith the external contact electrodes 220 of the second substrate 210.This is caused by a feature of the fabricating method that will bedescribed below. Further, the lead line 310 may extend outside thesecond substrate 210 and then be bent toward the first semiconductorpackage 100. Referring to FIG. 3B, a bending angle θ may be about 90° oran obtuse angle. However, since too great of an angle θ requires anoverly wide space for a connection between the first semiconductorpackage and the second semiconductor package, the bending angle θ may beabout 90° to about 120°.

According to another embodiment of the present invention, each externalcontact electrode 120 of the first substrate 110 may be in a form of ahole 120 b passing through the first substrate 110, as shown in FIG. 4A.That is, the hole 120 b passing through the first substrate 110 may befirst formed and then an external contact electrode 120 a may be formedto coat an inner surface of the hole 120 b. The external contactelectrodes 120 a coating the inner surface of the hole 120 b maypartially extend along the upper and lower surfaces of the firstsubstrate 110. The external contact electrode 120 may be connected withan end of a circuit (not shown) formed on the first substrate 110. FIG.4B illustrates a connection of the lead line 300 with the externalcontact electrode 120 of the first substrate 110. Referring to FIG. 4B,the lead line 300 is inserted into the external contact electrode 120and electrically connected thereto through, for example, a solder 122.

The lead line 300 may sufficiently extend through the external contactelectrode 120 of the first substrate 110 so as to be electricallyconnected with an external board, such as a main board. FIG. 5illustrates the lead lines 300 that pass through the external contactelectrodes 120 of the first substrate 110 and are directly connected tocontact electrodes 410 of the external board 400. The contact electrodes410 may be connected to an end of a circuit (not shown) formed on theexternal board 400.

The external contact electrodes 120′ of the first substrate 110 may beconnected with the contact electrodes 410 of the external board 400through, for example, solder balls 124.

The lead lines 300 may be connected with the contact electrodes 410 ofthe external board 400 in a standing form as shown in FIG. 5 or in agull-wing or J form as shown in FIGS. 6A and 6B.

According to another embodiment of the present invention, the externalcontact electrodes 220 of the second substrate 210 are formed in twolines along an outer perimeter of the lower surface 210 a of the secondsubstrate 210, in which the outer external contact electrodes and theinner external contact electrodes may be formed in a zigzag pattern.FIG. 7A illustrates the lower surface of the second substrate 210.Referring to FIG. 7A, the external contact electrodes 220 are formed asthe outer external contact electrodes 220 b and the inner externalcontact electrodes 220 a in two lines along the outer perimeter 211 ofthe second substrate 210 on the lower surface 210 a thereof.Particularly, the outer external contact electrodes 220 b and the innerexternal contact electrodes 220 a are formed in a zigzag pattern. Thiszigzag pattern allows lead lines connected to the inner external contactelectrodes 220 a to be easily connected with the first semiconductorpackage 100 without being brought into contact with lead lines connectedto the outer external contact electrodes 220 b, as shown in FIG. 7B.

According to another embodiment of the present invention, the externalcontact electrodes 220 of the second substrate 210 are formed in twolines 220 a and 220 b along the outer perimeter on the lower surface 210a of the second substrate 210, the lead lines 300 connected with theouter external contact electrodes 220 b in parallel with the lowersurface 210 a of the second substrate 210 extend outside of the secondsubstrate 210, are bent toward the first semiconductor package 100, andare connected to the external contact electrodes 120 of the firstsubstrate 110, and the lead lines 300 connected with the inner externalcontact electrodes 220 a in parallel with the lower surface 210 a of thesecond substrate 210 are bent toward the first semiconductor package andthen connected to the external contact electrodes 120 of the firstsubstrate 110. In other words, the lead lines 300 are first connected tothe external contact electrodes 220 in parallel with the lower surface210 a of the second substrate and then the lead lines 300 are bent so asto form an angle with the lower surface 210 a.

FIG. 8 is a side view schematically illustrating the above embodiment.Referring to FIG. 8, the external contact electrodes 220 are formed intwo lines 220 a and 220 b on the lower surface 210 a of the secondsemiconductor package 200. The external contact electrodes 220 a and 220b in the two lines are similar with those shown in FIG. 7A except thatthe inner external contact electrodes 220 a and the outer externalcontact electrodes 220 b do not have to be located in a zigzag pattern.

The first lead lines 300 a correspondingly connected with the innerexternal contact electrodes 220 a and the second lead lines 300 bcorrespondingly connected with the outer external contact electrodes 220b extend in parallel with the lower surface 210 a of the secondsubstrate 210. Then, the first lead lines 300 a and the second leadlines 300 b are bent toward the first semiconductor package 100 andconnected with the external contact electrodes 120 of the firstsubstrate 110.

All or at least some of the lead lines 300 a and 300 b may pass throughthe first substrate 110, extend to an external board on which the POPpackage including the first semiconductor package 100 and the secondsemiconductor package 200 is mounted, and can be connected with contactelectrodes on the external board.

In the above embodiments, at least one of the first semiconductorpackage and the second semiconductor package mounted in the POP packagemay be a multi-chip package (MCP).

A method of fabricating a POP package according to an embodiment of thepresent invention will now be described with reference to theaccompanying drawings.

First, the first semiconductor package 100 and the second semiconductorpackage 200 are prepared. The first semiconductor package 100 includesthe first substrate 110 and the first semiconductor chip 140 mounted onthe first substrate 110. The first substrate 110 may include theexternal contact electrodes 120. The first semiconductor chip 140 may bemounted on the first substrate 110 through, for example, wire-bonding,but the present invention is not limited thereto. The secondsemiconductor package 200 may be prepared using the same method as thefirst semiconductor package 100. The first semiconductor package 100 andthe second semiconductor package 200 may be formed as shown in FIGS. 1,3A, 5 and/or 8.

Then, as shown in FIG. 9, the external contact electrodes 220 of thesecond substrate 210 are aligned and electrically connected with thecorresponding lead lines 300, the second semiconductor package 200 isplaced on the first semiconductor package 100, and the lead lines areelectrically connected with the external contact electrodes 120 of thefirst substrate 110, such that the external contact electrodes 120 ofthe first substrate 110 and the external contact electrodes 220 of thesecond substrate 210 are electrically connected to each other.

The process of aligning and electrically connecting the external contactelectrodes 220 of the second substrate 210 with the lead lines 300 willbe described in detail with reference to FIGS. 10A through 10E.

Referring to FIGS. 10A and 10B, a lead frame 500 having lead lines 510formed thereon to correspond to the external contact electrodes of thesecond semiconductor package 200 is prepared and located under thesecond semiconductor package 200. FIG. 10C illustrates a cross-sectionof FIG. 10B. As shown in FIG. 10C, the external contact electrodes 220of the second substrate 210 are bonded to an end of the lead lines 510.For bonding, as an example, a conductive resin, a conductive tape or asolder may be used but the present invention is not limited thereto.

A point corresponding to location A of FIG. 10C is then cut out toseparate the second semiconductor package 200 having the lead lines 300bonded thereto from the lead frame 500 (FIG. 10D). As shown in FIG. 10E,the lead lines 300 are then bent so that they can be connected with theunderlying first semiconductor package 100.

Although the method for forming the lead lines by mounting onesemiconductor package on one lead frame is shown in FIGS. 10A through10E, lead lines may be formed in several semiconductor packages at onetime by coupling several lead frames as shown in FIG. 10A repeatedly andhorizontally and mounting the semiconductor packages on each lead framesubstantially simultaneously.

The step of preparing the second semiconductor package may includeforming external contact electrodes of the second substrate in two linesalong the outer perimeter of the second substrate on the lower surfacethereof. The external contact electrodes formed in two lines along theouter perimeter of the second substrate on the lower surface thereof areshown FIG. 7A, but they do not have to be necessarily formed in a zigzagpattern. Among the external contact electrodes in the two lines, theouter external contact electrodes are defined as first external contactelectrodes 220 b and the inner external contact electrodes are definedas second external contact electrodes 220 a.

Connecting the lead lines 300 with corresponding ones of the externalcontact electrodes 220 formed in two lines will be described. First, alead frame 600 as shown in FIG. 11 is prepared. The lead frame 600includes a lead frame support 650 and a punched portion 640 formedtherein, a pad 620 located at a center of the punched portion 640, abridge 630 for connecting the pad 620 to the lead frame support 650 andsupporting it, first lead lines 610 b formed along an inner perimeter ofthe punched portion 640 and corresponding to the first external contactelectrodes, and second lead lines 610 a formed along an outer perimeterof the pad 620 and corresponding to the second external contactelectrodes.

The second semiconductor package 200 is placed on the lead frame 600 asindicated by a dotted line in FIG. 11. The first external contactelectrodes of the second semiconductor package are bonded to the firstlead lines 610 b, particularly, portion B of FIG. 11, and the secondexternal contact electrodes are bonded to the second lead lines 610 a,particularly, portion A of FIG. 11.

FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 11.Referring to FIG. 12, the first lead lines 610 b of the lead frame 600are correspondingly connected to the first external contact electrodes220 b of the second semiconductor package 200, and the second lead lines610 a of the lead frame 600 are correspondingly connected to the secondexternal contact electrodes 220 a.

An end portion of the first lead lines 610 b directed outside the secondsemiconductor package 200 (“C” of FIG. 12) and an end portion of thesecond lead line 610 a directed inside the second semiconductor package200 (“D” of FIG. 12) are then cut out. A cutting result is shown in FIG.13, in which the lead lines 610 a and 610 b are formed on the externalcontact electrodes 220 a and 220 b, respectively.

The lead lines 610 a and 610 b may be then bent toward the firstsemiconductor package (downward in FIG. 13) and connected with the firstsemiconductor package. The lead lines 610 a and 610 b may be bent usinga typical method, but the present invention is not limited thereto.

The second semiconductor package 200 may be prepared by forming theexternal contact electrodes 220 of the second substrate 210 in two linesalong the outer perimeter of the second substrate 210 on the lowersurface thereof, with the outer external contact electrodes 220 andinner external contact electrodes 220 in the two lines arranged in azigzag pattern. After the second semiconductor package 200 is preparedas described above, lead lines may be formed using a lead frame 700 asshown in FIG. 14. Referring to FIG. 14, the lead frame 700 includes alead frame support 750 and a punched portion 740 formed therein, firstlead lines 710 b formed along an inner perimeter of the punched portion740 of the lead frame 700 and corresponding to the outer externalcontact electrodes 220 b of the second semiconductor package 200, andsecond lead lines 710 a corresponding to the inner external contactelectrodes 220 a and having a length greater than that of the first leadlines 710 b. Particularly, the first lead lines 710 b and the secondlead lines 710 a are alternately repeated and formed along the innerperimeter of the punched portion 740.

The second semiconductor package 200 is connected to the lead frame 700and the lead lines 710 a and 710 b are separated from the lead framesupport 750, such that the lead lines 710 a and 710 b are formed in thesecond semiconductor package 200. The lead lines 710 a and 710 b arethen bent toward the first semiconductor package 100 so that the secondsemiconductor package 200 is connected to the first semiconductorpackage 100.

Once connected as described above, the first semiconductor package 100and the second semiconductor package 200 form one POP package, which maybe mounted on the external board. To mount the POP package on theexternal board, the external contact electrodes formed in the firstsemiconductor package 100 may be connected with the contact electrodesformed on the external board through, for example, solder balls. Thefirst semiconductor package 100 of the POP package may be connected withthe external board by the lead lines 300 connecting the secondsemiconductor package 200 to the first semiconductor package 100extending to the external board by passing through the firstsemiconductor package 100 (See FIG. 5).

In other words, the external contact electrodes 120 of the firstsubstrate 110 are in the form of holes passing through the firstsubstrate 110, and the lead lines 300 pass through the external contactelectrodes 120 of the first substrate 110 when the external contactelectrodes 120 of the first substrate 110 and the external contactelectrodes 220 of the second substrate 210 are electrically connectedwith each other using the lead lines 300, such that the POP package isconnected with the external board.

In this case, the end of each lead line passing through the externalcontact electrode of the first substrate may be in a gull-wing form, a Jform, or a standing form. (See FIGS. 5, 6A and 6B).

Further, the first semiconductor package 100 may be directly connectedwith the external board through the solder balls 124.

According to the POP package and the fabricating method thereof of thepresent invention, the POP package is prevented from beingshort-circuited even when an underlying semiconductor package is thickand can sufficiently withstand deformation caused by post-fabricationwarpage.

According to an aspect of the present invention, there is provided apackage-on-package (POP) package including a first semiconductor packageincluding a first substrate having external contact electrodes and afirst semiconductor chip mounted on the first substrate; a secondsemiconductor package including a second substrate having externalcontact electrodes and a second semiconductor chip mounted on the secondsubstrate, the second semiconductor package being located on the firstsemiconductor package; and lead lines for electrically connecting theexternal contact electrodes of the first substrate to the externalcontact electrodes of the second substrate.

The connection between the first semiconductor package and the secondsemiconductor package through the lead lines eliminates the possibilitythat contact electrodes are short-circuited even when the firstsemiconductor package is thick and the semiconductor packages getsmaller. Furthermore, since the lead lines are stronger than solderballs in a bonding force and can well withstand the deformation of thesemiconductor package, defects caused by the warpage of thesemiconductor package can be reduced.

Particularly, the lead lines may be connected to the external contactelectrodes of the second substrate in parallel with the lower surface ofthe second substrate, extend outside the second substrate, be benttoward the first semiconductor package, and then be connected with theexternal contact electrode of the first substrate.

Further, the external contact electrodes of the first substrate may bein the form of holes passing through the first substrate, and the leadlines may pass through the external contact electrodes of the firstsubstrate so that the lead lines can be connected with an external boardon which the POP package is mounted. In this case, an end of each leadline may be in a gull-wing form, a J form, or a standing form.

Further, each lead line may be a bar or a pin.

The external contact electrodes of the second substrate may be formed intwo lines along an outer perimeter of the second substrate on the lowersurface thereof, and outer external contact electrodes and innerexternal contact electrodes in the two lines may be formed in a zigzagpattern.

The external contact electrodes of the second substrate may be formed intwo lines along an outer perimeter of the second substrate on the lowersurface thereof, the lead lines connected with the outer externalcontact electrodes in parallel with the lower surface of the secondsubstrate may extend outside the second substrate, are bent toward thefirst semiconductor package, and be connected with the external contactelectrodes of the first substrate, and the lead lines connected withinner external contact electrodes in parallel with the lower surface ofthe second substrate may be bent toward the first semiconductor packageand then connected with the external contact electrodes of the firstsubstrate.

The external contact electrodes of the first semiconductor package mayinclude at least one solder ball for connection to a board on which thePOP package is mounted.

Further, at least one of the first semiconductor package and the secondsemiconductor package may be a multi-chip package (MCP).

According to another aspect of the present invention, there is provideda method of fabricating a package-on-package (POP) package, the methodincluding preparing a first semiconductor package including a firstsubstrate having external contact electrodes and a first semiconductorchip mounted on the first substrate; preparing a second semiconductorpackage including a second substrate having external contact electrodesand a second semiconductor chip mounted on the second substrate; forminglead lines in the second semiconductor package, the lead lines beingelectrically connected to the external contact electrodes of the secondsubstrate; and placing the second semiconductor package on the firstsemiconductor package and electrically connecting the external contactelectrodes of the first substrate to the external contact electrodes ofthe second substrate using the lead lines.

The forming of lead lines in the second semiconductor package mayinclude bonding the second semiconductor package to a lead frame, thelead frame including a plurality of lead lines corresponding to theexternal contact electrodes of the second semiconductor package;separating the lead lines from the lead frame; and bending the leadlines toward the first semiconductor package when the firstsemiconductor package and the second semiconductor package are stackedto each other.

In this case, the preparing of a second semiconductor package mayinclude forming the external contact electrodes of the second substratein two lines along the outer perimeter of the second substrate on thelower surface thereof When the outer external contact electrodes aredefined as first external contact electrodes and the inner externalcontact electrode are defined as second external contact electrodes, thelead frame may include a lead frame support and a punched portion formedtherein; a pad located at a center of the punched portion; a bridge forconnecting the pad to the lead frame support and supporting the pad;first lead lines formed along an inner perimeter of the punched portionand corresponding to the first external contact electrodes; and secondlead lines formed along an outer perimeter of the pad and correspondingto the second external contact electrodes. Furthermore, the separatingof the lead lines from the lead frame may include cutting an end portionof the first lead line directed outside the second semiconductorpackage; and cutting an end portion of the second lead line directedinside the second semiconductor package.

The preparing of a second semiconductor package may include forming theexternal contact electrodes of the second substrate in two lines alongthe outer perimeter of the second substrate on the lower surfacethereof, with outer external contact electrodes and inner externalcontact electrodes in the two lines zigzagged. In this case, the leadframe may include a lead frame support and a punched portion formedtherein; first lead lines and corresponding to the outer externalcontact electrodes; and second lead lines corresponding to the innerexternal contact electrodes and having a length greater than that of thefirst lead lines, wherein the first lead lines and the second lead linesare alternately repeated and formed along an inner perimeter of thepunched portion.

The bonding of the second semiconductor package to a lead frame may beperformed using a conductive resin, conductive tape, or solder.

The external contact electrodes of the first substrate may be in theform of holes passing through the first substrate, and electricallyconnecting the external contact electrodes of the first substrate to theexternal contact electrodes of the second substrate using the lead linesmay include passing the lead lines through the external contactelectrodes of the first substrate and connecting the lead lines to anexternal board on which the POP package is mounted. In this case, theend of each lead line passing through the external contact electrode ofthe first substrate may be in a gull-wing form, a J form, or a standingform.

The method may further include forming solder balls in the externalcontact electrodes of the first semiconductor package to connect the POPpackage with an external board.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A method of fabricating a package-on-package (POP) package, themethod comprising: preparing a first semiconductor package including afirst substrate having external contact electrodes and a firstsemiconductor chip mounted on the first substrate; preparing a secondsemiconductor package including a second substrate having externalcontact electrodes and a second semiconductor chip mounted on the secondsubstrate; forming lead lines in the second semiconductor package, thelead lines being electrically connected to the external contactelectrodes of the second substrate; and stacking the secondsemiconductor package on the first semiconductor package andelectrically connecting the external contact electrodes of the firstsubstrate to the external contact electrodes of the second substrateusing the lead lines.
 2. The method of claim 1, wherein the forming oflead lines in the second semiconductor package comprises: bonding thesecond semiconductor package to a lead frame, the lead frame including aplurality of lead lines corresponding to the external contact electrodesof the second semiconductor package; separating the lead lines from thelead frame; and bending the lead lines toward the first semiconductorpackage when the first semiconductor package and the secondsemiconductor package are stacked.
 3. The method of claim 2, whereinbending the lead lines comprises bending the lead lines so as to form anangle of about 90° to about 120°.
 4. The method of claim 2, wherein thepreparing of a second semiconductor package comprises forming theexternal contact electrodes of the second substrate in two lines alongthe outer perimeter of the second substrate on a lower surface thereof,the external contact electrodes comprise outer external contactelectrodes and inner external contact electrodes, the outer externalcontact electrodes are defined as first external contact electrodes andthe inner external contact electrodes are defined as second externalcontact electrodes, the lead frame comprises: a lead frame support and apunched portion formed therein; a pad located at a center of the punchedportion; a bridge for connecting the pad to the lead frame support andsupporting the pad; first lead lines formed along an inner perimeter ofthe punched portion and corresponding to the first external contactelectrodes; and second lead lines formed along an outer perimeter of thepad and corresponding to the second external contact electrodes; and theseparating of the lead lines from the lead frame comprises: cutting anend portion of the first lead lines directed outside the secondsemiconductor package; and cutting an end portion of the second leadlines directed inside the second semiconductor package.
 5. The method ofclaim 2, wherein the preparing of a second semiconductor packagecomprises forming the external contact electrodes of the secondsubstrate in two lines along the outer perimeter of the second substrateon the lower surface thereof, with outer external contact electrodes andinner external contact electrodes in the two lines arranged in a zigzagpattern.
 6. The method of claim 5, wherein the lead frame comprises: alead frame support and a punched portion formed therein; first leadlines corresponding to the outer external contact electrodes; and secondlead lines corresponding to the inner external contact electrodes andhaving a length greater than that of the first lead lines, wherein thefirst lead lines and the second lead lines are alternately repeated andformed along an inner perimeter of the punched portion.
 7. The method ofclaim 2, wherein the bonding of the second semiconductor package to alead frame is performed using a conductive resin, conductive tape, orsolder.
 8. The method of claim 1, wherein the external contactelectrodes of the first substrate are in the form of holes passingthrough the first substrate, and electrically connecting the externalcontact electrodes of the first substrate to the external contactelectrodes of the second substrate using the lead lines comprisespassing the lead lines through the external contact electrodes of thefirst substrate and connecting the lead lines to an external board onwhich the POP package is mounted.
 9. The method of claim 8, wherein theend of each lead line passing through the external contact electrode ofthe first substrate is in a gull-wing form, a J form, or a standingform.
 10. The method of claim 1, further comprising forming solder ballson the external contact electrodes of the first semiconductor package toconnect the POP package with an external board.